
Hey, i couldn't answer Hugh's question at this evening's meeting off the top of my head, but wikipedia to the rescue: https://en.wikipedia.org/wiki/ARM_Cortex-M#Instruction_sets "All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply." I was much more involved with cortex-m SoCs in the earlier days but wasn't 100% sure of the instruction sets of the latest members of the family but, according to wikipedia, all cortex-m's use some variant of the thumb instruction set. Best regards, Trevor

On Tue, Jan 11, 2022 at 09:37:45PM -0500, Trevor Woerner via talk wrote:
i couldn't answer Hugh's question at this evening's meeting off the top of my head, but wikipedia to the rescue: https://en.wikipedia.org/wiki/ARM_Cortex-M#Instruction_sets
"All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply."
I was much more involved with cortex-m SoCs in the earlier days but wasn't 100% sure of the instruction sets of the latest members of the family but, according to wikipedia, all cortex-m's use some variant of the thumb instruction set.
Yes the Cortex-M lines have none of the standard arm instruction set. Thunmb2 seems very good though, and as far as I understand it, the armhf architecture runs almost entirely thumb2 code for the 32 bit Cortex-A chips. 64 bit arm (aarch64) appears to be essentially the 32 bit arm instructions, although conditional execution feature seems to be almost entirely gone. It was a neat feature but probably was getting in the way. -- Len Sorensen
participants (2)
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Lennart Sorensen
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Trevor Woerner