[GTALUG] Western Digital's open source RISC-V core

I assume that you can put this on a FPGA, as Chris Tyler talked about on Tuesday. I haven't checked this. I think that it is in verilog, but I'm not sure. <https://github.com/westerndigitalcorporation/swerv_eh1> There's also an emulator: <https://github.com/westerndigitalcorporation/swerv-ISS> I have no idea if there is MMU support in the core (needed for reasonable Linux).