
21 May
2016
21 May
'16
11:48 a.m.
On 05/21/2016 01:33 PM, D. Hugh Redelmeier wrote:
A RISC processor would not have a complex instruction decoder so this kind of hacking would not apply. I will admit that there are "hazards" in RISC processors that are worth paying attention to when selecting and ordering instructions but these tend to be clearer.
Many years ago, I used to maintain Data General Eclipse systems. The CPU used microcode to control AMD bit slice processors and associated logic. The microcode instructions were over 100 bits wide. Now *THAT'S* RISC. ;-) BTW, those CPUs had an option called Writable Control Store (WCS) where one could create custom instructions.