
On 05/22/2016 12:03 PM, Lennart Sorensen wrote:
Many years ago, I used to maintain Data General Eclipse systems. The CPU used microcode to control AMD bit slice processors and associated logic. The microcode instructions were over 100 bits wide. Now *THAT'S* RISC. ;-)
BTW, those CPUs had an option called Writable Control Store (WCS) where one could create custom instructions. That sounds more like the opposite of RISC. Much more like VAX or
On Sat, May 21, 2016 at 02:48:50PM -0400, James Knott wrote: mainframes used to be as far as I know. Maybe even VLIW, although probably not.
Now being able to define new instructions using low level RISC features might make some sense, although how much the savings would be in execution time or binary size I don't know. I have a hard time imagining much gain there.
The real laugh is that RISC processors most often have more instructions than CISC processors. Can you consider the JVM a CISC machine? -- Alvin Starr || voice: (905)513-7688 Netvel Inc. || Cell: (416)806-0133 alvin@netvel.net ||