On Thu, Feb 12, 2015 at 06:26:16PM -0600, Russell Reiter wrote:
Three billion transistors require a mighty robust memory management subsystem. Given the development costs of these chip sets and other factors of parallel advancements in existing architectures, a few false starts are to be expected. Who knows maybe all this belongs in the tomorrow file.
Instruction replay RAS and other improvements for checking and correcting errors, are most certainly desirable features. Fine grained exit status is essential for lockstepping cache threads and compile time predication looks like it could be efficient enough for reducing transport delay. Just need better ram with fewer flaws or perhaps parallel RAS and journal the bad bits. ECC or not its the uncommon errors which need to be predicated.
So now the problem is not limited to things like voltage flux, it's far field interference like background radiation which tend to flip the bits.
What do any of those have to do with VLIW? They apply equality to CISC and RISC as well, but at least those tend to be designed to run real code generated by real compilers rather than imagined code generated by imagined magical compilers that don't exist. -- Len Sorensen